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The role involves driving go-to-market strategies, creating technical marketing content, and fostering a community around quantum products.

Lead invention of AI-driven ASIC development methodology, identify cross-stage bottlenecks, build scalable data pipelines, define metrics, mentor engineers, and evaluate AI/EDA research to improve predictability and cycle time.

The Senior Formal Verification Engineer will verify ASICs using formal verification methods, ensuring correctness and collaborating with architects and designers across projects.

As a Senior ASIC Design Engineer, you will design high performance RTL, collaborate with teams, and analyze architectural trade-offs for ASICs and GPUs.