Lead technical design and delivery of scalable full-stack applications while remaining hands-on with backend systems, workflow orchestration, event-driven architectures, microservices, and APIs. Mentor engineers, guide technical direction, and own engineering outcomes across cloud-based applications and CI/CD pipelines.

Remote 12-month contract RTL Design Engineer to own micro-architecture and RTL implementation for complex digital blocks. Requires SystemVerilog/Verilog expertise, memory controller and SoC integration experience, IP integration, multi-clock-domain design, and sign-off familiarity (CDC/RDC/lint/synthesis). Works independently and collaborates with DV for closure and debug.