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This role involves stimulus development for CPU microarchitecture in a hybrid work environment, requiring collaboration with design and verification teams.

The Staff RTL Core Engineer will design RTL and microarchitecture for high-performance silicon, collaborating with various teams to ensure quality delivery and debug issues in both pre and post-silicon environments.

The engineer will focus on CPU core feature verification, testing plans, designs, and debugging of simulation and emulation regressions for high-performance CPUs.

Develop and optimize emulation infrastructure for high-performance AI/ML systems, ensuring robust debugging and efficiency while mentoring junior engineers.

Conduct DFT implementation for high-performance chip designs, optimizing tests and collaborating on ASIC development while managing complex engineering tasks.

As a Functional Simulation Architect, you will develop virtual platforms for CPU, ML Accelerators, and manage model enhancements for co-development.

Manage and maintain CRM, handle sales data, create quotes, and support sales operations to ensure efficiency and accuracy.