The CAD/Flow Methodology Development leader will define and scale EDA infrastructure, automate design flows, debug issues, and establish metrics for silicon delivery efficiency in cross-functional environments.

The Design Verification Engineer ensures functional correctness of IPs and SoCs by developing verification environments, driving coverage closure, and automating tasks to enhance productivity.

Drive end-to-end execution of semiconductor programs, ensuring alignment across teams, managing risks, and meeting customer commitments with high quality.