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Designs advanced ASIC packages, including FC-BGA and MCM architectures, from early trade studies through production. Responsibilities include substrate and ball-map definition, SI/PI and thermal design, high-speed signal breakout, material and assembly selection, vendor management, qualification, and collaboration with silicon, RF, and systems teams. The role focuses on high-pin-count, power-dense mixed-signal and digital SoC packages for high-reliability aerospace applications.

Lead end-to-end ASIC package architecture and execution for high-performance FC-BGA and MCM solutions. Own substrate stackups, ball maps, SI/PI, thermal design, material selection, vendor qualification, packaging standards, and production ramp. Partner with silicon, RF, and systems teams to optimize package interfaces and ensure reliable, first-pass success for high-pin-count, power-dense mixed-signal and digital ASICs.

Leads the architecture, circuit design, integration, verification, tapeout, and silicon validation of high-speed ADCs, DACs, and analog front-ends for advanced mixed-signal SoCs. The role covers converter trade studies, FinFET CMOS circuit implementation, calibration, clocking, references, signal integrity, and DSP collaboration. It also provides technical leadership, establishes design methodologies, and mentors analog and mixed-signal engineers.

Lead full physical design flow for complex SoC blocks and top-level integration from synthesis to GDSII. Drive timing closure, PPA optimization, physical sign-off (DRC/LVS, IR drop, EM), ECOs and tapeout. Collaborate with front-end, verification, DFT, packaging teams and external vendors, develop automation and methodology, and support products through production and spaceflight.

Lead end-to-end RTL-to-GDSII physical design for high-performance SoCs in advanced FinFET nodes. Own synthesis, floorplanning, P&R, CTS, STA, DRC/LVS and sign-off; develop methodologies and automation to optimize PPA; drive timing closure, coordinate package/SI/PI and DFT, manage external PD partners and EDA tool flows, and support post-silicon bring-up and production for spaceflight-qualified designs.

Lead verification of custom ASIC/SoC from block to full-chip: develop verification plans, build SystemVerilog/UVM testbenches, run constrained-random and directed tests, use SVA and formal methods, manage regressions and CI, drive coverage closure, support post-silicon bring-up, and influence DV methodology across cross-functional teams.

Lead DFT architecture and implementation for complex mixed-signal SoCs. Responsible for RTL-level scan and BIST insertion, ATPG flow development and coverage closure, mixed-signal test strategies, DFT verification and signoff, silicon bring-up support, and methodology/automation improvements while collaborating with design, verification, and physical design teams.

Define and execute verification plans for block-to-full-chip ASICs using SystemVerilog/UVM. Build testbenches, assertions, constrained-random and directed tests, manage regressions and CI, run simulations, triage failures, close coverage, and support silicon bring-up and post-silicon debug while collaborating across architecture, RTL, DFT, firmware, and physical design teams.

Own FPGA prototyping and silicon bring-up for next-generation communications ASICs. Build FPGA-based platforms, support first-silicon debug, validate high-speed interfaces, develop automated test infrastructure, and collaborate across ASIC, firmware, software, and systems teams.