Lead digital design of mixed-signal RAIN RFID Reader ICs from architecture through tapeout and silicon validation. Develop micro-architectures, executable models, and RTL; collaborate with RF/analog, physical design, verification, and CAD teams. Define DFT and low-power strategies, drive timing closure and synthesis, support post-silicon bring-up, and improve design flows and methodologies while mentoring junior engineers.

Lead RTL verification for RAIN RFID reader ICs across product lifecycle. Develop verification methodologies, SystemVerilog/UVM testbenches, BFMs, assertions, coverage metrics, CI/CD automation, and constrained-random tests. Collaborate with digital, analog, and silicon teams to ensure tape-out quality and support post-silicon validation and product improvements.

Lead full-chip and transistor-level RF/mixed-signal layout for RFID and reader ICs, own floorplanning and tapeout readiness, coordinate cross-functional teams, perform DRC/LVS/DFM/EMIR reviews, mentor layout engineers, and drive layout methodology and foundry integration through production tape-outs.