Senior Staff Engineer, Physical Design

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a Senior Staff Physical Design Engineer at Marvell Technology, you will be a key part of a highly skilled global team focused on designing next-generation high-performance processor chips. Our custom Processor/ASIC solutions power critical infrastructure in markets such as server, 5G/6G, and networking. You will work at the forefront of advanced CMOS process technology, contributing to both physical design and the development of efficient design methodologies. This role allows you to collaborate with a diverse, innovative team that spans across geographies.

What You Can Expect

In this role, you will play an essential part in developing and implementing the physical design flow for Marvell’s high-performance, cutting-edge chips. You’ll work on synthesis, place and route, and timing analysis for intermediate and complex logic blocks, ensuring that they meet Marvell’s stringent performance, power, and area targets. Furthermore you’ll be involved in full-chip floorplanning, partition and design planning activities. By enhancing and maintaining the Place and Route flow using industry-standard EDA tools, you’ll enable seamless tape-outs and help drive Marvell’s continued leadership in the semiconductor industry.
 

Your collaboration with the RTL design and global timing teams will ensure smooth end-to-end design processes and successful delivery of best-in-class products. As the industry evolves, your contributions to methodologies will drive optimization and innovation for future technologies.
 

What Can You Expect

• • Physical Design Execution: Perform synthesis, floor planning, place and route, clock tree synthesis, and timing analysis on complex blocks. You will ensure that designs meet performance, power, and area goals across advanced technology nodes like 7nm, 5nm and 3nm.

  • Methodology Development: Work on Place and Route methodology for efficient and robust design processes, enhancing Marvell’s physical design flow. You will be tasked with maintaining and supporting these methodologies to ensure continued improvements in efficiency and accuracy.

  • Timing and Logic ECOs: Develop and implement timing and logic Engineering Change Orders (ECOs) while closely collaborating with RTL teams to address congestion and timing issues.

  • Cross-functional Collaboration: Work closely with the frontend design and global timing teams to resolve block-level timing issues, ensuring a smooth tape-out process.

  • Innovative Challenges: Tackle complex, multi-disciplinary challenges and play a key role in driving technology advancements in automotive, 5G/6G, networking, and server chip designs. Your role is a critical interface between backend design, frontend design, and methodology teams.

What We're Looking For

• Educational Background: Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience. Coursework and projects must include digital logic design, circuit testing, and timing analysis.
• Professional Experience: At least 2 years of related experience in physical design, with a proven track record of successful tape-outs, preferably top-level implementation. Experience with advanced technology nodes such as 7nm, 5nm, or below is highly desirable. Experience with chiplet-based architectures and full-chip physical design a plus. Experience in static timing analysis (STA), with a focus on timing closure and signoff using PrimeTime is highly desirable.
• Hands-On Expertise: Strong experience with industry-standard EDA tools, including synthesis, floor planning, place and route, clock tree synthesis, timing closure, and physical verification.
• Physical Design Methodologies: Proven experience working with RTL-to-GDS flows, including experience with digital logic and computer architecture using Verilog/VHDL. Familiarity with timing analysis and congestion resolution is crucial.
• Scripting Skills: Demonstrable proficiency in scripting languages such as Perl, tcl, and Python for automation and workflow enhancement.
• Communication & Teamwork: Excellent communication skills and a proven ability to work effectively in a collaborative, team-oriented environment.
• Problem-Solving: Ability to troubleshoot and resolve complex timing and physical design issues at block and partition levels.

Expected Base Pay Range (USD)

125,900 - 186,260, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

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