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NVIDIA

Senior Physical Verification Engineer, VLSI Implementation

Posted Yesterday
Be an Early Applicant
In-Office or Remote
6 Locations
136K-265K Annually
Senior level
In-Office or Remote
6 Locations
136K-265K Annually
Senior level
Develop physical verification methodologies for GPUs and SOCs, focusing on DRC, LVS, and antenna flows, while ensuring tape-out success and collaboration with design teams.
The summary above was generated by AI

Today, we are tapping into the unlimited potential of AI to define the next era of computing. An era in which NVIDIA’s GPUs act as the brains of computers, robots, and self-driving cars that can understand the world. Doing what has never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you will be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Come join our dynamic team and see how you can make a lasting impact on the world!

We are currently looking for a Sr VLSI Physical Verification Methodology Engineer.

What you'll be doing:

  • Developing physical verification methodologies for implementation of graphics processors and SOCs.

  • Responsible for physical verification and debugging of reticle-sized chips, and for coordinating with the PNR team to achieve SOL tape-out.

  • Participate in developing physical verification flows for new technologies - DRC, LVS, Antenna flows - improving automation and expert workflows.

  • Work with design teams to improve overall DRC feedback and correlation improvement.

  • TSMC A16 rules and tape-out experience is preferred.

What we need to see:

  • BS/MS in Electrical Engineering or related field (or equivalent experience) 

  • Minimum 4+ years of physical implementation experience with 2+ years in physical verification.

  • Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification. 

  • Strong knowledge and experience with Physical Verification debug of shorts/compare results across DRC/LVS/Antenna related issues in both PV signoff tools as well as EDA implementation tools (ICC2/Innovus/other)

  • Direct experience with ICV and Calibre runsets for physical verification of DRC/LVS/Antenna.

  • Proficient in writing DRC/LVS rules, including advanced checks tailored to specific design requirements for ICV and CALIBRE tools.

  • Good scripting and programming skills in Python/Perl or other related automation languages.

Ways to stand out from the crowd:

  • Exposure to Virtuoso or ICWeb platforms , AI application to PV analysis or workflows, workflow automation experience.

     

NVIDIA is widely considered to be one of the technology world’s most desirable employers, and due to outstanding success, our teams are rapidly growing. Are you passionate about joining a best-in-class team driving the latest in EDA, GPU, and AI technology? If so, we want to hear from you!

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 7, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Top Skills

Calibre
Eda Tools
Icc2
Icv
Innovus
Perl
Python
Tsmc A16

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