Senior Engineer - Hardware Modeling

Code Metal is redefining code translation for mission-critical industries, helping defense partners move more quickly and reliably from algorithm to silicon. Our platform accelerates deployment of DSP, RF, communications, and embedded signal processing algorithms onto heterogeneous compute targets, including GPUs, FPGAs, ASICs, and edge SoCs. We also support automotive, aerospace, and semiconductor partners deploying complex algorithms onto constrained hardware with speed and rigor.

The Role
We are now looking for a Senior Engineer – Hardware Modeling to help expand our core product into the world of AI-assisted hardware design and SystemC modeling. This is a unique opportunity to shape how advanced AI workflows integrate with EDA tools and chip design processes. If you’re passionate about hardware modeling and want to be at the forefront of how AI is transforming EDA and chip design, we’d love to hear from you.

• Architect Agentic AI Pipelines: Partner with AI and software teams to automate the generation, refinement, and validation of RTL models.
• Optimize Development Velocity: Build robust infrastructure to streamline emulation workloads, significantly reducing turnaround times and hardware development cycles.
• Orchestrate EDA Integration: Drive AI-driven modeling workflows within industry-standard EDA environments to accelerate simulation, emulation, and synthesis.
• Eligible to obtain and maintain an active U.S. Top Secret security clearance.

• Education & Experience: M.S. with 5+ years or B.S. with 8+ years of industry experience in semiconductor domain.
• Advanced Emulation/Prototyping: 3+ years of hands-on expertise in large-scale SoC or IP emulation and prototyping using industry-standard platforms (e.g., Synopsys ZeBu/HAPS, Cadence Palladium/Protium, or Siemens EDA Veloce).
• Deep Silicon Bringup Expertise: 5+ years of extensive experience in full-chip bringup and sophisticated RTL debug using advanced tools such as Verdi, nWave, SimVision, Verisium, or Visualizer.
• Architecture & Design Fundamentals: Solid grasp of digital design, SoC architecture, and mastery of SystemVerilog/Verilog.
• Advanced Verification Methodologies: Proven capability in developing C/C++ DPI transactors, Accelerated UVM testbenches, SVA (SystemVerilog Assertions), and SpeedBridges; demonstrated success in firmware bringup.
• Protocol Proficiency: Deep understanding of high-speed and debug protocols and interfaces, including PCIe, DDR, AXI, I2C, UART, JTAG, etc.
• Testbench Innovation: Experience implementing scalable testbenches for complex multi-die/chiplet environments, utilizing advanced transactors and performance monitors.
• Automation & Tooling: Expert-level proficiency in scripting (Python, Tcl, Bash/tcsh, Makefile) to build and maintain automation frameworks that boost productivity.
• Disciplined Execution: Exceptional ability to plan and execute structured experiments (DoE), perform data-driven analysis, and synthesize complex findings for stakeholders.
• AI/SW Collaboration: Proven track record of cross-functional collaboration with software teams to refine and maintain agentive AI workflows.
• Formal Verification: Hands-on experience with Formal Verification techniques to complement simulation/emulation-based validation.
• Active U.S. security clearance (Secret or Top-Secret).

• Pay depends on experience, but we strive to be at the upper end of the salary range

• Health care plan with 100% premium coverage, including medical, dental, and vision
• 401k with 5% matching
• Paid Time Off (uncapped vacation, plus sick and public holidays)
• Flexible hybrid or remote work arrangement
• Relocation assistance for qualifying employees

We are an equal opportunity employer. US Citizenship may be required for certain project assignments involving security clearance.