CPU Performance Architect, Cache Subsystem

Tenstorrent is looking for a CPU Performance Architect focused on the cache subsystem to help shape the performance of our next-generation CPUs. You’ll work alongside world-class architecture talent to design, model, and analyze how cache subsystems impact system behavior and application-level performance. This is a great role for someone who enjoys digging deep into simulation data, understanding the tradeoffs of cache design, and influencing decisions from early design to implementation. Join us to build a performant, scalable computer that redefines what modern CPUs can do—across chiplets, interconnects, and memory systems.

This role is hybrid, based out of Santa Clara, CA, Austin, TX, Boston, MA, or Remote in the United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are: 

• You’ve got a strong foundation in computer architecture, especially around cache hierarchies, coherence protocols, and memory subsystem performance.
• You’re hands-on with cycle-accurate simulation tools like Gem5 or similar, and comfortable working in C++ for performance modeling and analysis.
• You enjoy performance exploration—profiling, debugging, and iterating until a system hits its goals.
• You're a strong communicator who can clearly explain architectural tradeoffs to cross-functional teams.
• Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science with at least three years of industry experience, or a Ph.D. in a related field.

What We Need: 

• Help design and optimize the cache subsystem, including controllers and coherence protocol behavior.
• Conduct performance modeling and analysis of the cache subsystem to guide architecture and implementation choices.
• Collaborate with software, RTL, and interconnect teams to understand real-world memory access patterns and tune for efficiency.
• Stay current on trends in memory tech (e.g., DDR, HBM) and interconnect protocols (e.g., CHI, AXI, PCIe, CXL) to inform and evolve our architecture.

What You Will Learn: 

• How to connect early-stage performance modeling with final silicon behavior through deep architecture-design-validation collaboration.
• How cache coherence and memory subsystem design influence power, performance, and scalability in chiplet-based CPUs.
• How Tenstorrent leverages parallelism and custom architecture to build CPUs for AI, HPC, and beyond.
• How to balance cutting-edge hardware design with system-level software optimizations for real workloads.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.